1. Field of the Invention
This invention relates to a CMOS integrated circuit, and more particularly to protection of a CMOS integrated circuit from a breakdown when the so-called latch-up phenomenon is generated.
2. Description of the Prior Art
The CMOS integrated circuit is composed of N- and P-channel MOS field effect transistors (hereinafter, referred to as N- and P-MOS FET's) one of which is formed in a semiconductor substrate of one conductivity type and the another of which is formed in a will region of other conductivity type which is formed in the semiconductor substrate. The structure inherently involves many parasitic transistors. For example, if an N type substrate and a P type well region are used, the source region of the P-MOS FET, the substrate and the well region form a PNP bipolar transistor and the source region of the N-MOS FET, the well region and the substrate form an NPN transistor. Besides, those PNP and NPN transistors equivalently form a PNPN thyristor. Another PNP bipolar transistor is formed by the source region of the P-MOS FET, the substrate and the well region. The former and latter PNP bipolar transistors have common base and collector regions. A positive power voltage is supplied to the substrate, while the well region is supplied with a grounding potential. The drain regions of the P-and N-MOS FET's are connected to an output terminal.
If a noise having a positive voltage higher than the power supply voltage is applied to the output terminal, the latter PNP bipolar transistor turns on. The collector current flows to the grounding point of the well region. This current biases the NPN bipolar transistor to turn on by the resistive component of the well region. The collector current of the NPN bipolar transistor flows to the power supplying point and biases the former PNP bipolar transistor to turn on by the resistive component of the substrate. By turning on the NPN and former PNP bipolar transistors, the PNPN thyristor turns on to lower the impedance between the power supplying and grounding points. The thus lowered impedance allows a large current to flow though the substrate and the well region. This current becomes 10 to 50 times the operating current and causes the thermal breakdown of PN junctions and the melt of wiring metal. This is known as the latch-up phenomenon and is peculiar to the CMOS integrated circuit.